1. Field of the Invention
The invention relates to a memory, and more particularly to a static random access memory.
2. Description of the Related Art
Typical memory devices include read only memory (ROM) and random access memory (RAM). When power is interrupted, ROM data remains and RAM data is eliminated. RAM comprises dynamic random access memory (DRAM) and static random access memory (SRAM).
Each DRAM comprises a plurality of memory cells, each comprising a capacitor such that a refresh circuit is required to cyclically charge the capacitor to maintain the voltage of the capacitor. Each SRAM is formed by a plurality of transistors such that the SRAM is faster. The SRAM does not require a refresh circuit.
In deep submicron technology, SRAM is a commonly used storage unit suitable for high speed, low power, communication or system on chip (SOC) products.
FIG. 1 is a schematic diagram of a conventional static random access memory. A static random access memory 10 comprises six transistors. Since a larger leakage current is generated in static random access memory 10, the operating voltage VDD is reduced by a conventional solution. When the operating voltage VDD is reduced, a read margin of static random access memory 10 is also reduced.